Chapter 3 PL reads and writes DDR4 experiment through NoC#
The experimental VIvado project is “pl_rw_ddr”.
Hardware introduction#
The PL side of the development board has 4 16bit ddr4
Vivado project set up#
Versal’s DDR4 is accessed through NoC, so NoC IP needs to be added for configuration.
Create a Block design and configure the NoC#
Select Create Block Design
Add CIPS
Double-click CIPS, select PL_Subsystem, only the logic on the PL side
Add NoC IP
Configure NoC
Select an AXI Slave and AXI Clock, select “Single Memory Controller”
Select Inputs as PL
connection port
DDR4 configuration
Configuration is complete, click OK
Configure CIPS and add reset
Click Finish
Add Clocking Wizard and configure the output clock to 150MHz as the PL side read and write clock
8) Add IBUFDS for NoC and Clocking Wizard provides a reference clock and exports S00_AXI, CH0_DDR4_0 and other buses, and adds axi_clk and axi_resetn to provide clock and reset for the PL side.
Double-click the reference clock pin and configure the frequency to 200MHz
Double-click the AXI bus and configure
Assign address
Create HDL
Add additional test code#
The main function of other codes is to read and write ddr4 and compare whether the data is consistent. I will not introduce it in detail here. You can refer to the engineering code.
Add mark_debug debugging in mem_test.v
Pin binding
Comprehensive
After the synthesis is completed, click Set up debug
Set the number of sampling points according to needs
Then save and generate pdi file
Download debugging#
After generating the pdi file, use JTAG to download it to the development board, and DDR4 calibration and other information will be displayed in the MIG_1 window.
Debug signals can be viewed in hw_ila_1
Experiment summary#
This experiment directly reads and writes ddr4 through the PL side Verilog code. It mainly understands the configuration method of NoC and how to access DDR4 through NoC. This configuration will be used in subsequent experiments.