Ctrl+K

Chapter 5 GTYP transceiver bit error rate test IBERT experiment

Chapter 5 GTYP transceiver bit error rate test IBERT experiment#

The experimental VIvado project is “ibert_test”, and there is also “ibert_ex” in the directory, which is the generated test project.

Vidado software provides us with the powerful bit error rate tester IBERT, which can not only test the bit error rate but also test the eye diagram, which brings great convenience to us in using high-speed transceivers. This experiment will serve as a starting point and briefly introduce the IBERT use.

Hardware introduction#

To use IBERT to test the bit error rate and eye diagram, you must have transceiver loopback hardware. There are two SFP optical interfaces on the development board. In this experiment, the two optical interfaces are connected in pairs to form two transceiver loopthrough links.

Vivado project set up#

  1. Create a new project named “ibert_test”

2) Search “gt” in “IP Catalog” to quickly find “Versal ACAPs Transceivers” Wizard”, double-click

../_images/image133.png

  1. Change “Component Name” to “ibert” and modify the preset to “Aurora 64B/66B”

../_images/image134.png

  1. Click Transceiver Configs Protocol 0, configure the sending and receiving parameters, and click OK

../_images/image135.png ../_images/image136.png ../_images/image137.png

  1. Click Generate

../_images/image138.png

  1. Right-click “Open IP Example Design…” and select the example project path

../_images/image139.png ../_images/image140.png

  1. Add buffer to connect to apb3clk

../_images/image1411.png

  1. Add inverter connected to reset

../_images/image142.png

  1. Some other signals are configured as constant 0

../_images/image143.png

  1. Delete output signal

../_images/image144.png

  1. Configure sfp_disable to 0

../_images/image145.png

  1. Change CIPS to PL Subsystem

../_images/image146.png

  1. Constraint pins

../_images/image147.png

  1. Generate pdi file

../_images/image148.png

Download debugging#

  1. Insert the optical module, then use optical fiber to connect the two optical ports, connect the JTAG download cable, and power on the development board

../_images/image149.png

  1. Use JTAG to download the BIT file to the development board. You can see that the speed is close to 10.3125Gbps.

../_images/image150.png

  1. Select IBERT, right-click and select “Create Links”

../_images/image1511.png

Referring to the schematic diagram, the optical fiber is connected to CH0 and CH1 of Quad104. Select Link 0 as Quad_104 CH_0 TX corresponds to CH1 RX, Link 1 corresponds to Quad_104 CH_1 TX and CH0 RX

../_images/image152.png

  1. Modify the configuration, select PRBS 31 for the code stream, and configure Loopback to None

../_images/image153.png

  1. After configuration, you can click BERT Reset. You can see that the Errors are all 0 and restart the test.

../_images/image154.png

  1. Select a link, right-click “Create Scan…”

../_images/image155.png ../_images/image156.png

  1. The eye diagram configured by default. Note: The measured eye diagram may be different when using different software versions.

../_images/image157.png
目录