Chapter 6 Experience ARM, bare metal output “Hello World”#
From this chapter onwards, FPGA engineers and software development engineers collaborate to implement it.
The previous experiments were all conducted on the PL side. It can be seen that there is no difference from the ordinary FPGA development process. The main advantage of ZYNQ is the reasonable combination of FPGA and ARM, which puts forward higher requirements for developers. Starting from this chapter, we start to use ARM, which is what we call PS. In this chapter, we use a simple serial port printing to experience Vivado Vitis and PS side features.
The previous experiments are all things that FPGA engineers should do. From the beginning of this chapter, there is a division of labor. FPGA engineers are responsible for setting up the Vivado project and providing good hardware to software developers. Software developers can develop applications on this basis. . A good division of labor is also conducive to the advancement of the project. If a software developer wants to do everything, it may take a lot of time and energy to learn FPGA knowledge. Converting from software thinking to hardware thinking is a relatively painful process. If you just want to learn purely and have time, you can That’s another matter. Professional people doing professional things is a good choice.
Hardware introduction#
We can see from the schematic diagram that the ZYNQ chip is divided into PL and PS. The IO allocation on the PS side is relatively fixed and cannot be allocated arbitrarily, and there is no need to allocate pins in the Vivado software. Although this experiment only used PS, it still To create a Vivado project to configure PS pins. Although the ARM on the PS side is a hard core, in ZYNQ the ARM hard core must be added to the project before it can be used. The previous chapters introduced projects in the form of codes. This chapter begins by introducing ZYNQ’s graphical approach to building projects.
FPGA engineer job content#
The following introduces what FPGA engineers are responsible for.
Vivado project set up#
1) Create a project named “ps_hello”. The establishment process will not be described in detail. Please refer to “PL’s” Hello World “LED Experiment”.
Click “Create Block Design” to create a Block design
3) “Design name” is not modified here, keep the default “design_1”, you can modify it as needed, but the name should be as short as possible, otherwise there will be problems compiling under Windows.
Click the “Add IP” shortcut icon
5) Search for “PS” and double-click “Control, Interfaces & Processing” in the search results list System”
Click Run Block Automation
Configure as follows, click OK
Automatic connection is as follows
Double-click CIPS to configure
select PS PMC to config
Config QSPI，EMMC，SD
Select the corresponding MIO
Check USB 2.0, GEM0, UART0, TTC, GPIO and other peripherals
Configure peripherals
Configure MIO24 as GPIO input, corresponding to the PS side buttons, and configure MIO25 as GPIO output, corresponding to the PS side LED lights
In clocking, set the reference clock more accurately
Check all internal interrupts, the configuration is complete, and click OK
Click Finish
Double-click AXI NoC to configure DDR4
select reference clock and system clock
DDR Address Region 1, select NONE and OK
Modify pin name
Double-click to configure the frequency of sys_clk to 200MHz
Select the Block design, right-click “Create HDLWrapper…”, create a Verilog or VHDL file for blockdesign generates HDL top-level files.
Keep the default options and click “OK”
Add constraint
Generate Device Image
Cancel after completion
File->Export->Export Hardware…
At this time, you can see the xsa file in the project directory. This file contains Vivado hardware design information and can be used by software developers.
At this point, the work of the FPGA engineer comes to an end.
Software engineer job content#
The Vitis project directory is “ps_hello/vitis”
The following is the responsibility of software engineers.
Debugging#
Create Application project#
Create a new folder and copy the xx.xsa file exported by vivado.
2) Vitis is an independent software. You can double-click the Vitis software to open it, or select ToolsLaunch in the Vivado software. VitisOpen Vitis software
On the welcome interface, click Open Workspace, select the previously created folder, and click “OK”
3) After starting Vitis, the interface is as follows, click “Create Platform” Component”, this option will create a Platform project, which is similar to previous versions of hardware platform, including hardware support related files and BSP.
Fill in the Component name and path on the first page, keep the default, and click Next
Select (XSA, select “Browse”, select the previously generated xsa, click to open, and then click Next
Select operating system and processor, keep the default here
Click Finish to complete
After generation, a window interface appears. The following are some window introductions. They are similar to the previous version of Vitis interface, but the differences are also quite large.
The platform can be compiled in the Flow window
no error status
10) Click Example on the left. There are many official routines here, which are similar to previous versions. Select Hello. World
Click to create project
Fill in the project name and path and keep the default
Select the platform
Click Next
Complete
Select hello_world and click Build
Download debugging#
Connect the JTAG cable to the development board and the UART USB cable to the PC
Before powering on, it is best to set the startup mode of the development board to JTAG mode and pull it to the “ON” position.
Power on the development board, open the serial port debugging tool, and click Run in Flow
At this time, observe the serial port debugging tool and you can see the output “Hello World”
firmware#
Ordinary FPGAs can generally be started from flash or passively loaded. The startup process has been introduced in the PMC architecture in Chapter 1 and will not be introduced here.
Select Create Boot in Flow Image, you can see the generated BIF file path in the pop-up window. The BIF file is the configuration file for generating the BOOT file, and the generated Output Image file path, that is, the BOOT.pdi file is generated. It is the startup file we need. It can be placed in the SD card for startup, or it can be programmed to QSPI. Flash.
The boot.pdi file can be found in the generated directory
SD card boot test#
Format the SD card. It can only be formatted to FAT32 format. Other formats cannot be started.
Put the boot.pdi file into the root directory
Insert the SD card into the SD card slot of the development board
Adjust the startup mode to SD card startup
Open the serial port software, power on and start, you can see the printed information. The red box is the FSBL startup information, and the yellow arrow part is the executed application helloworld.
QSPI startup test#
In the Vitis menu Vitis -> Program Flash
2) Select the boot.pdi to be burned in the Image FIle file. Select Verify after flash, Flash Select qspi-x8-dual_parallel for Type, and verify the flash after programming is completed.
Click Program and wait for programming to complete
Set the startup mode to QSPI, start it again, and you can see the same startup effect as SD in the serial port software.
chapter summary#
This chapter introduces the classic process of Versal development from the perspectives of both FPGA engineers and software engineers. The main job of FPGA engineers is to build a hardware platform and provide hardware description files xsa to software engineers, who then develop applications based on this. This chapter is a simple example that introduces the collaborative work of FPGA and software engineers. It will also involve joint debugging between PS and PL later, which is more complicated and is also the core part of Versal development.
At the same time, FSBL, startup file production, SD card startup method, QSPI download and startup method are also introduced.